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advance information this data sheet states amd?s current technical specifications regarding the products described herein. this data sheet may be revised by subsequent versions or modifications due to changes in technical specifications. publication# 25270 rev: b amendment/ +3 issue date: december 2, 2002 refer to amd?s website (www.amd.com) for the latest information. am29lv128m 128 megabit (8 m x 16-bit/16 m x 8-bit) mirrorbit ? 3.0 volt-only uniform sector flash memory with versatilei/o ? control distinctive characteristics architectural advantages single power supply operation ? 3 volt read, erase, and program operations versatilei/o ? control ? device generates data output voltages and tolerates data input voltages on the ce# and dq inputs/outputs as determined by the voltage on the v io pin; operates from 1.65 to 3.6 v manufactured on 0.23 m mirrorbit process technology secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer flexible sector architecture ? two hundred fifty-six 32 kword (64 kbyte) sectors compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125 c performance characteristics high performance ? 90 ns access time ? 25 ns page read times ? tbd- typical sector erase time ? tbd- typical write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? 4-word/8-byte page read buffer ? 16-word/32-byte write buffer low power consumption (typical values at 3.0 v, 5 mhz) ? 30 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current package options ? 56-pin tsop ? 64-ball fortified bga software & hardware features software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word or byte programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector group unprotect: v id -level method of changing code in locked sector groups ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion
2 am29lv128m december 2, 2002 advance information general description the am29lv128m is a 128 mbit, 3.0 volt single power supply flash memory devices organized as 8,388,608 words or 16,777,216 bytes. the device has a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the byte# input. the device can be programmed either in the host system or in standard eprom programmers. an access time of 90, 100, 110, or 120 ns is available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide and the order- ing information sections. the device is offered in a 56-pin tsop, 64-ball fortified bga. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased current. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. the sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase oper- ation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to deter- mine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. the versatilei/o? (v io ) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the ce# control input and dq i/os to the same voltage level that is asserted on the v io pin. refer to the ordering information section for valid v io options. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector group protection feature disables both program and erase operations in any combination of sector groups of memory. this can be achieved in-system or via pro- gramming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the pro- gram operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. the write protect (wp# /acc ) feature protects the first or last sector by asserting a logic low on the wp# pin. amd mirrorbit flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection. related documents for a comprehensive information on mirrorbit prod- ucts, including migration information, data sheets, ap- plication notes, and software drivers, please see www.amd.com flash memory product informa- tion mirrorbit flash information technical docu- mentation. the following is a partial list of documents closely related to this product: mirrorbit? flash memory write buffer programming and page buffer read implementing a common layout for amd mirrorbit and intel strataflash memory devices migrating from single-byte to three-byte device ids am29lv256m, 256 mbit mirrorbit flash device (in 64-ball, 18 x 12 mm fortified bga package)
december 2, 2002 am29lv128m 3 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . 8 device bus operations . . . . . . . . . . . . . . . . . . . . . 9 table 1. device bus operations ....................................................... 9 word/byte configuration .......................................................... 9 versatileio ? (v io ) control ....................................................... 9 requirements for reading array data ................................... 10 page mode read ............................................................................10 writing commands/command sequences ............................ 10 write buffer .....................................................................................10 accelerated program operation ......................................................10 autoselect functions .......................................................................10 standby mode ........................................................................ 10 automatic sleep mode ........................................................... 11 reset#: hardware reset pin ............................................... 11 output disable mode .............................................................. 11 table 2. sector address table........................................................ 12 autoselect mode ..................................................................... 18 table 3. autoselect codes, (high voltage method) ....................... 18 sector group protection and unprotecti on ............................. 19 table 4. sector group protection/unprotection address table ..... 19 write protect (wp#) ................................................................ 20 temporary sector group u nprotect ....................................... 20 figure 1. temporary sector group unprotect operation ................20 figure 2. in-system sector group protect/unprotect algorithms ...21 secsi (secured silicon) sector flash memory region .......... 22 table 5. secsi sector contents ...................................................... 22 figure 3. secsi sector protect verify ..............................................23 hardware data protection ...................................................... 23 low vcc write inhibit .....................................................................23 write pulse ?glitch? protection ........................................................23 logical inhibit ..................................................................................23 power-up write inhibit ....................................................................23 common flash memory interface (cfi) . . . . . . . 23 table 6. cfi query identification string ..........................................24 table 7. system interface string..................................................... 24 table 8. device geometry definition ..............................................25 table 9. primary vendor-specific extended query ........................26 command definitions . . . . . . . . . . . . . . . . . . . . . 27 reading array data ................................................................ 27 reset command ..................................................................... 27 autoselect command sequence ............................................ 27 enter secsi sector/exit secsi sector command sequence .. 28 word/byte program command sequence ............................. 28 unlock bypass command sequence ..............................................28 write buffer programming ...............................................................28 accelerated program ......................................................................29 figure 4. write buffer programming operation ...............................30 figure 5. program operation ..........................................................31 program suspend/program resume command sequence ... 31 figure 6. program suspend/program resume ...............................32 chip erase command sequence ........................................... 32 sector erase command sequence ........................................ 32 figure 7. erase operation ...............................................................33 erase suspend/erase resume comma nds ........................... 33 command definitions ............................................................. 34 table 10. command definitions (x16 mode, byte# = v ih ) ........... 34 table 11. command definitions (x8 mode, byte# = v il ).............. 35 write operation status . . . . . . . . . . . . . . . . . . . . . 36 dq7: data# polling ................................................................. 36 figure 8. data# polling algorithm .................................................. 36 ry/by#: ready/busy# ............................................................ 37 dq6: toggle bit i .................................................................... 37 figure 9. toggle bit algorithm ........................................................ 38 dq2: toggle bit ii ................................................................... 38 reading toggle bits dq6/dq2 ............................................... 38 dq5: exceeded timing limits ................................................ 39 dq3: sector erase timer ....................................................... 39 dq1: write-to-buffer abort ..................................................... 39 table 12. write operation status................................................... 40 absolute maximum ratings. . . . . . . . . . . . . . . . . 41 figure 10. maximum negative overshoot waveform ................... 41 figure 11. maximum positive overshoot waveform ..................... 41 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 41 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 12. test setup .................................................................... 43 table 13. test specifications ......................................................... 43 key to switching waveforms. . . . . . . . . . . . . . . . 43 figure 13. input waveforms and measurement levels ................. 43 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 read-only operations .................. ......................................... 44 figure 14. read operation timings ............................................... 44 figure 15. page read timings ...................................................... 45 hardware reset (reset#) .................................................... 46 figure 16. reset timings ............................................................... 46 erase and program operations .............................................. 47 figure 17. reset timings ............................................................... 48 figure 18. program operation timings .......................................... 49 figure 19. accelerated program timing diagram .......................... 49 figure 20. chip/sector erase operation timings .......................... 50 figure 21. data# polling timings (during embedded algorithms) . 51 figure 22. toggle bit timings (during embedded algorithms) ...... 52 figure 23. dq2 vs. dq6 ................................................................. 52 temporary sector group unprotect ....................................... 53 figure 24. temporary sector group unprotect timing diagram ... 53 figure 25. sector group protect and unprotect timing diagram .. 54 alternate ce# controlled eras e and program operations ..... 55 figure 26. alternate ce# controlled write (erase/program) operation timings .......................................................................... 56 latchup characteristics . . . . . . . . . . . . . . . . . . . . 56 erase and programming performance. . . . . . . . 57 tsop pin and bga package capacitance . . . . . 57 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 58 ts056/tsr056?56-pin standard/reverse thin small outline package (tsop) ..................................................................... 58 laa064?64-ball fortified ball grid array 13 x 11 mm package .............................................................. 59 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 60
4 am29lv128m december 2, 2002 advance information product selector guide notes: 1. see ?ac characteristics? for full specifications. block diagram part number am29lv128m speed/ voltage option regulated voltage range v cc = 3.0?3.6 v 93r v io = 3.0?3.6 v 103r v io = 2.7?3.6 v 113r v io = 1.65?3.6 v 123r v io = 1.65?3.6 v full voltage range v cc = 2.7?3.6 v 103 v io = 2.7?3.6 v 113 v io = 1.65?3.6 v 123 v io = 1.65?3.6 v max. access time (ns) 90 100 110 120 max. ce# access time (ns) 90 100 110 120 max. page access time (t pa cc ) 2530304030 40 max. oe# access time (ns) 25 30 30 40 30 40 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc byte# ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a22?a0 v io
december 2, 2002 am29lv128m 5 advance information connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io 56-pin standard tsop 56-pin reverse tsop
6 am29lv128m december 2, 2002 advance information connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc nc v ss v io nc a22 nc 64- ball fortified bga top view, balls facing down
december 2, 2002 am29lv128m 7 advance information pin description a22?a0 = 23 address inputs dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input; acceleration input reset# = hardware reset pin input byte# = selects 8-bit or 16-bit mode ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally logic symbol 23 16 or 8 dq15?dq0 (a-1) a22?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte#
8 am29lv128m december 2, 2002 advance information ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am29lv128m h 93r pc i temperature range i = industrial (?40 c to +85 c) package type e = 56-pin thin small outline package (tsop) standard pinout (ts 056) f = 56-pin thin small outline package (tsop) reverse pinout (tsr056) pc = 64-ball fortified ball grid array ( f bga), 1.0 mm pitch, 13 x 11 mm package (laa064) speed option see product selector guide and valid combinations sector architecture and sector write protection (wp# = v il ) h = uniform sector device, highest address sector protected l = uniform sector device, lowest address sector protected device number/description am29lv128mh/l 128 megabit (8 m x 16-bit/16 m x 8-bit) mirrorbit uniform sector flash memory with versatileio ? control, 3.0 volt-only read, program, and erase valid combinations for tsop package speed (ns) v io range v cc range am29lv128mh93r am29lv128ml93r ei, fi 90 3.0?3.6 v 3.0?3.6 v am29lv128mh103 am29lv128ml103 100 2.7?3.6 v 2.7?3.6 v am29lv128mh113 am29lv128ml113 110 1.65?3.6 v am29lv128mh123 am29lv128ml123 120 1.65?3.6 v am29lv128mh103r am29lv128ml103r 100 2.7?3.6 v 3.0?3.6 v am29lv128mh113r am29lv128ml113r 110 1.65?3.6 v am29lv128mh123r am29lv128ml123r 120 1.65?3.6 v valid combinations for fortified bga package speed (ns) v io range v cc range order number package marking am29lv128mh93r am29lv128ml93r pci l128mh93n l128ml93n i 90 3.0? 3.6 v 3.0? 3.6 v am29lv128mh103 am29lv128ml103 l128mh103p l128ml103p 100 2.7? 3.6 v 2.7? 3.6 v am29lv128mh113 am29lv128ml113 l128mh113p l128ml113p 110 1.65? 3.6 v am29lv128mh123 am29lv128ml123 l128mh123p l128ml123p 120 1.65? 3.6 v am29lv128mh103r am29lv128ml103r l128mh103n l128ml103n 100 2.7? 3.6 v 3.0? 3.6 v am29lv128mh113r am29lv128ml113r l128mh113n l128ml113n 110 1.65? 3.6 v am29lv128mh123r am29lv128ml123r l128mh123n l128ml123n 120 1.65? 3.6 v
december 2, 2002 am29lv128m 9 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a22:a0 in word mode; a22:a-1 in byte mode. sector addresses are a22:a15 in both modes. 2. the sector group protect and sector group unprotect functions may also be implemented via programming equipment. see the ?sector group protection and unprotection? section. 3. if wp# = v il , the first or last sector remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 4. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word con- figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. versatileio ? (v io ) control the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ordering information for v io options on this device. operation ce# oe# we# reset# wp# acc addresses (note 2) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h xx a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 3) x a in (note 4) (note 4) accelerated program l h l h (note 3) v hh a in (note 4) (note 4) standby v cc 0.3 v xx v cc 0.3 v xh x high-z high-z high-z output disable l h h h xx x high-z high-z high-z reset x x x l xx x high-z high-z high-z sector group protect (note 2) lhl v id hx sa, a6 =l, a3=l, a2=l, a1=h, a0=l (note 4) x x sector group unprotect (note 2) lhl v id hx sa, a6=h, a3=l, a2=l, a1=h, a0=l (note 4) x x temporary sector group unprotect xxx v id hx a in (note 4) (note 4) high-z
10 am29lv128m december 2, 2002 advance information requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only operations table for timing spec- ifications and to figure 14 for the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. the page size of the device is 4 words/8 bytes. the appropriate page is selected by the higher address bits a(max)?a2. ad- dress bits a1?a0 in word mode (a1?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode ac- cesses are obtained by keeping the ?read-page ad- dresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facil- itate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word/byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command se- quences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac char- acteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is prima- rily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to re- duce the time required for program operations. the system would use a two-cycle program command se- quence as required by the unlock bypass mode. re- moving v hh from the wp#/acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose- lect command sequence sections for more informa- tion. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than
december 2, 2002 am29lv128m 11 advance information v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device re- quires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. refer to the dc characteristics table for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard ad- dress access timings provide new data when ad- dresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the dc characteristics table for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# pa- rameters and to figure 16 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
12 am29lv128m december 2, 2002 advance information table 2. sector address table sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 00000000 64/32 000000?00ffff 000000?007fff sa1 00000001 64/32 010000?01ffff 008000?00ffff sa2 00000010 64/32 020000?02ffff 010000?017fff sa3 00000011 64/32 030000?03ffff 018000?01ffff sa4 00000100 64/32 040000?04ffff 020000?027fff sa5 00000101 64/32 050000?05ffff 028000?02ffff sa6 00000110 64/32 060000?06ffff 030000?037fff sa7 00000111 64/32 070000?07ffff 038000?03ffff sa8 00001000 64/32 080000?08ffff 040000?047fff sa9 00001001 64/32 090000?09ffff 048000?04ffff sa10 00001010 64/32 0a0000?0affff 050000?057fff sa11 00001011 64/32 0b0000?0bffff 058000?05ffff sa12 00001100 64/32 0c0000?0cffff 060000?067fff sa13 00001101 64/32 0d0000?0dffff 068000?06ffff sa14 00001110 64/32 0e0000?0effff 070000?077fff sa15 00001111 64/32 0f0000?0fffff 078000?07ffff sa16 00010000 64/32 100000?10ffff 080000?087fff sa17 00010001 64/32 110000?11ffff 088000?08ffff sa18 00010010 64/32 120000?12ffff 090000?097fff sa19 00010011 64/32 130000?13ffff 098000?09ffff sa20 00010100 64/32 140000?14ffff 0a0000?0a7fff sa21 00010101 64/32 150000?15ffff 0a8000?0affff sa22 00010110 64/32 160000?16ffff 0b0000?0b7fff sa23 00010111 64/32 170000?17ffff 0b8000?0bffff sa24 00011000 64/32 180000?18ffff 0c0000?0c7fff sa25 00011001 64/32 190000?19ffff 0c8000?0cffff sa26 00011010 64/32 1a0000?1affff 0d0000?0d7fff sa27 00011011 64/32 1b0000?1bffff 0d8000?0dffff sa28 00011100 64/32 1c0000?1cffff 0e0000?0e7fff sa29 00011101 64/32 1d0000?1dffff 0e8000?0effff sa30 00011110 64/32 1e0000?1effff 0f0000?0f7fff sa31 00011111 64/32 1f0000?1fffff 0f8000?0fffff sa32 00100000 64/32 200000?20ffff 100000?107fff sa33 00100001 64/32 210000?21ffff 108000?10ffff sa34 00100010 64/32 220000?22ffff 110000?117fff sa35 00100011 64/32 230000?23ffff 118000?11ffff sa36 00100100 64/32 240000?24ffff 120000?127fff sa37 00100101 64/32 250000?25ffff 128000?12ffff sa38 00100110 64/32 260000?26ffff 130000?137fff sa39 00100111 64/32 270000?27ffff 138000?13ffff sa40 00101000 64/32 280000?28ffff 140000?147fff sa41 00101001 64/32 290000?29ffff 148000?14ffff sa42 00101010 64/32 2a0000?2affff 150000?157fff sa43 00101011 64/32 2b0000?2bffff 158000?15ffff sa44 00101100 64/32 2c0000?2cffff 160000?167fff sa45 00101101 64/32 2d0000?2dffff 168000?16ffff sa46 00101110 64/32 2e0000?2effff 170000?177fff
december 2, 2002 am29lv128m 13 advance information sa47 00101111 64/32 2f0000?2fffff 178000?17ffff sa48 00110000 64/32 300000?30ffff 180000?187fff sa49 00110001 64/32 310000?31ffff 188000?18ffff sa50 00110010 64/32 320000?32ffff 190000?197fff sa51 00110011 64/32 330000?33ffff 198000?19ffff sa52 00110100 64/32 340000?34ffff 1a0000?1a7fff sa53 00110101 64/32 350000?35ffff 1a8000?1affff sa54 00110110 64/32 360000?36ffff 1b0000?1b7fff sa55 00110111 64/32 370000?37ffff 1b8000?1bffff sa56 00111000 64/32 380000?38ffff 1c0000?1c7fff sa57 00111001 64/32 390000?39ffff 1c8000?1cffff sa58 00111010 64/32 3a0000?3affff 1d0000?1d7fff sa59 00111011 64/32 3b0000?3bffff 1d8000?1dffff sa60 00111100 64/32 3c0000?3cffff 1e0000?1e7fff sa61 00111101 64/32 3d0000?3dffff 1e8000?1effff sa62 00111110 64/32 3e0000?3effff 1f0000?1f7fff sa63 00111111 64/32 3f0000?3fffff 1f8000?1fffff sa64 01000000 64/32 400000?40ffff 200000?207fff sa65 01000001 64/32 410000?41ffff 208000?20ffff sa66 01000010 64/32 420000?42ffff 210000?217fff sa67 01000011 64/32 430000?43ffff 218000?21ffff sa68 01000100 64/32 440000?44ffff 220000?227fff sa69 01000101 64/32 450000?45ffff 228000?22ffff sa70 01000110 64/32 460000?46ffff 230000?237fff sa71 01000111 64/32 470000?47ffff 238000?23ffff sa72 01001000 64/32 480000?48ffff 240000?247fff sa73 01001001 64/32 490000?49ffff 248000?24ffff sa74 01001010 64/32 4a0000?4affff 250000?257fff sa75 01001011 64/32 4b0000?4bffff 258000?25ffff sa76 01001100 64/32 4c0000?4cffff 260000?267fff sa77 01001101 64/32 4d0000?4dffff 268000?26ffff sa78 01001110 64/32 4e0000?4effff 270000?277fff sa79 01001111 64/32 4f0000?4fffff 278000?27ffff sa80 01010000 64/32 500000?50ffff 280000?287fff sa81 01010001 64/32 510000?51ffff 288000?28ffff sa82 01010010 64/32 520000?52ffff 290000?297fff sa83 01010011 64/32 530000?53ffff 298000?29ffff sa84 01010100 64/32 540000?54ffff 2a0000?2a7fff sa85 01010101 64/32 550000?55ffff 2a8000?2affff sa86 01010110 64/32 560000?56ffff 2b0000?2b7fff sa87 01010111 64/32 570000?57ffff 2b8000?2bffff sa88 01011000 64/32 580000?58ffff 2c0000?2c7fff sa89 01011001 64/32 590000?59ffff 2c8000?2cffff sa90 01011010 64/32 5a0000?5affff 2d0000?2d7fff sa91 01011011 64/32 5b0000?5bffff 2d8000?2dffff sa92 01011100 64/32 5c0000?5cffff 2e0000?2e7fff sa93 01011101 64/32 5d0000?5dffff 2e8000?2effff sa94 01011110 64/32 5e0000?5effff 2f0000?2f7fff table 2. sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
14 am29lv128m december 2, 2002 advance information sa95 01011111 64/32 5f0000?5fffff 2f8000?2fffff sa96 01100000 64/32 600000?60ffff 300000?307fff sa97 01100001 64/32 610000?61ffff 308000?30ffff sa98 01100010 64/32 620000?62ffff 310000?317fff sa99 01100011 64/32 630000?63ffff 318000?31ffff sa100 01100100 64/32 640000?64ffff 320000?327fff sa101 01100101 64/32 650000?65ffff 328000?32ffff sa102 01100110 64/32 660000?66ffff 330000?337fff sa103 01100111 64/32 670000?67ffff 338000?33ffff sa104 01101000 64/32 680000?68ffff 340000?347fff sa105 01101001 64/32 690000?69ffff 348000?34ffff sa106 01101010 64/32 6a0000?6affff 350000?357fff sa107 01101011 64/32 6b0000?6bffff 358000?35ffff sa108 01101100 64/32 6c0000?6cffff 360000?367fff sa109 01101101 64/32 6d0000?6dffff 368000?36ffff sa110 01101110 64/32 6e0000?6effff 370000?377fff sa111 01101111 64/32 6f0000?6fffff 378000?37ffff sa112 01110000 64/32 700000?70ffff 380000?387fff sa113 01110001 64/32 710000?71ffff 388000?38ffff sa114 01110010 64/32 720000?72ffff 390000?397fff sa115 01110011 64/32 730000?73ffff 398000?39ffff sa116 01110100 64/32 740000?74ffff 3a0000?3a7fff sa117 01110101 64/32 750000?75ffff 3a8000?3affff sa118 01110110 64/32 760000?76ffff 3b0000?3b7fff sa119 01110111 64/32 770000?77ffff 3b8000?3bffff sa120 01111000 64/32 780000?78ffff 3c0000?3c7fff sa121 01111001 64/32 790000?79ffff 3c8000?3cffff sa122 01111010 64/32 7a0000?7affff 3d0000?3d7fff sa123 01111011 64/32 7b0000?7bffff 3d8000?3dffff sa124 01111100 64/32 7c0000?7cffff 3e0000?3e7fff sa125 01111101 64/32 7d0000?7dffff 3e8000?3effff sa126 01111110 64/32 7e0000?7effff 3f0000?3f7fff sa127 01111111 64/32 7f0000?7fffff 3f8000?3fffff sa128 10000000 64/32 800000?80ffff 400000?407fff sa129 10000001 64/32 810000?81ffff 408000?40ffff sa130 10000010 64/32 820000?82ffff 410000?417fff sa131 10000011 64/32 830000?83ffff 418000?41ffff sa132 10000100 64/32 840000?84ffff 420000?427fff sa133 10000101 64/32 850000?85ffff 428000?42ffff sa134 10000110 64/32 860000?86ffff 430000?437fff sa135 10000111 64/32 870000?87ffff 438000?43ffff sa136 10001000 64/32 880000?88ffff 440000?447fff sa137 10001001 64/32 890000?89ffff 448000?44ffff sa138 10001010 64/32 8a0000?8affff 450000?457fff sa139 10001011 64/32 8b0000?8bffff 458000?45ffff sa140 10001100 64/32 8c0000?8cffff 460000?467fff sa141 10001101 64/32 8d0000?8dffff 468000?46ffff sa142 10001110 64/32 8e0000?8effff 470000?477fff table 2. sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
december 2, 2002 am29lv128m 15 advance information sa143 10001111 64/32 8f0000?8fffff 478000?47ffff sa144 10010000 64/32 900000?90ffff 480000?487fff sa145 10010001 64/32 910000?91ffff 488000?48ffff sa146 10010010 64/32 920000?92ffff 490000?497fff sa147 10010011 64/32 930000?93ffff 498000?49ffff sa148 10010100 64/32 940000?94ffff 4a0000?4a7fff sa149 10010101 64/32 950000?95ffff 4a8000?4affff sa150 10010110 64/32 960000?96ffff 4b0000?4b7fff sa151 10010111 64/32 970000?97ffff 4b8000?4bffff sa152 10011000 64/32 980000?98ffff 4c0000?4c7fff sa153 10011001 64/32 990000?99ffff 4c8000?4cffff sa154 10011010 64/32 9a0000?9affff 4d0000?4d7fff sa155 10011011 64/32 9b0000?9bffff 4d8000?4dffff sa156 10011100 64/32 9c0000?9cffff 4e0000?4e7fff sa157 10011101 64/32 9d0000?9dffff 4e8000?4effff sa158 10011110 64/32 9e0000?9effff 4f0000?4f7fff sa159 10011111 64/32 9f0000?9fffff 4f8000?4fffff sa160 10100000 64/32 a00000?a0ffff 500000?507fff sa161 10100001 64/32 a10000?a1ffff 508000?50ffff sa162 10100010 64/32 a20000?a2ffff 510000?517fff sa163 10100011 64/32 a30000?a3ffff 518000?51ffff sa164 10100100 64/32 a40000?a4ffff 520000?527fff sa165 10100101 64/32 a50000?a5ffff 528000?52ffff sa166 10100110 64/32 a60000?a6ffff 530000?537fff sa167 10100111 64/32 a70000?a7ffff 538000?53ffff sa168 10101000 64/32 a80000?a8ffff 540000?547fff sa169 10101001 64/32 a90000?a9ffff 548000?54ffff sa170 10101010 64/32 aa0000?aaffff 550000?557fff sa171 10101011 64/32 ab0000?abffff 558000?55ffff sa172 10101100 64/32 ac0000?acffff 560000?567fff sa173 10101101 64/32 ad0000?adffff 568000?56ffff sa174 10101110 64/32 ae0000?aeffff 570000?577fff sa175 10101111 64/32 af0000?afffff 578000?57ffff sa176 10110000 64/32 b00000?b0ffff 580000?587fff sa177 10110001 64/32 b10000?b1ffff 588000?58ffff sa178 10110010 64/32 b20000?b2ffff 590000?597fff sa179 10110011 64/32 b30000?b3ffff 598000?59ffff sa180 10110100 64/32 b40000?b4ffff 5a0000?5a7fff sa181 10110101 64/32 b50000?b5ffff 5a8000?5affff sa182 10110110 64/32 b60000?b6ffff 5b0000?5b7fff sa183 10110111 64/32 b70000?b7ffff 5b8000?5bffff sa184 10111000 64/32 b80000?b8ffff 5c0000?5c7fff sa185 10111001 64/32 b90000?b9ffff 5c8000?5cffff sa186 10111010 64/32 ba0000?baffff 5d0000?5d7fff sa187 10111011 64/32 bb0000?bbffff 5d8000?5dffff sa188 10111100 64/32 bc0000?bcffff 5e0000?5e7fff sa189 10111101 64/32 bd0000?bdffff 5e8000?5effff sa190 10111110 64/32 be0000?beffff 5f0000?5f7fff table 2. sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
16 am29lv128m december 2, 2002 advance information sa191 10111111 64/32 bf0000?bfffff 5f8000?5fffff sa192 11000000 64/32 c00000?c0ffff 600000?607fff sa193 11000001 64/32 c10000?c1ffff 608000?60ffff sa194 11000010 64/32 c20000?c2ffff 610000?617fff sa195 11000011 64/32 c30000?c3ffff 618000?61ffff sa196 11000100 64/32 c40000?c4ffff 620000?627fff sa197 11000101 64/32 c50000?c5ffff 628000?62ffff sa198 11000110 64/32 c60000?c6ffff 630000?637fff sa199 11000111 64/32 c70000?c7ffff 638000?63ffff sa200 11001000 64/32 c80000?c8ffff 640000?647fff sa201 11001001 64/32 c90000?c9ffff 648000?64ffff sa202 11001010 64/32 ca0000?caffff 650000?657fff sa203 11001011 64/32 cb0000?cbffff 658000?65ffff sa204 11001100 64/32 cc0000?ccffff 660000?667fff sa205 11001101 64/32 cd0000?cdffff 668000?66ffff sa206 11001110 64/32 ce0000?ceffff 670000?677fff sa207 11001111 64/32 cf0000?cfffff 678000?67ffff sa208 11010000 64/32 d00000?d0ffff 680000?687fff sa209 11010001 64/32 d10000?d1ffff 688000?68ffff sa210 11010010 64/32 d20000?d2ffff 690000?697fff sa211 11010011 64/32 d30000?d3ffff 698000?69ffff sa212 11010100 64/32 d40000?d4ffff 6a0000?6a7fff sa213 11010101 64/32 d50000?d5ffff 6a8000?6affff sa214 11010110 64/32 d60000?d6ffff 6b0000?6b7fff sa215 11010111 64/32 d70000?d7ffff 6b8000?6bffff sa216 11011000 64/32 d80000?d8ffff 6c0000?6c7fff sa217 11011001 64/32 d90000?d9ffff 6c8000?6cffff sa218 11011010 64/32 da0000?daffff 6d0000?6d7fff sa219 11011011 64/32 db0000?dbffff 6d8000?6dffff sa220 11011100 64/32 dc0000?dcffff 6e0000?6e7fff sa221 11011101 64/32 dd0000?ddffff 6e8000?6effff sa222 11011110 64/32 de0000?deffff 6f0000?6f7fff sa223 11011111 64/32 df0000?dfffff 6f8000?6fffff sa224 11100000 64/32 e00000?e0ffff 700000?707fff sa225 11100001 64/32 e10000?e1ffff 708000?70ffff sa226 11100010 64/32 e20000?e2ffff 710000?717fff sa227 11100011 64/32 e30000?e3ffff 718000?71ffff sa228 11100100 64/32 e40000?e4ffff 720000?727fff sa229 11100101 64/32 e50000?e5ffff 728000?72ffff sa230 11100110 64/32 e60000?e6ffff 730000?737fff sa231 11100111 64/32 e70000?e7ffff 738000?73ffff sa232 11101000 64/32 e80000?e8ffff 740000?747fff sa233 11101001 64/32 e90000?e9ffff 748000?74ffff sa234 11101010 64/32 ea0000?eaffff 750000?757fff sa235 11101011 64/32 eb0000?ebffff 758000?75ffff sa236 11101100 64/32 ec0000?ecffff 760000?767fff sa237 11101101 64/32 ed0000?edffff 768000?76ffff sa238 11101110 64/32 ee0000?eeffff 770000?777fff table 2. sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
december 2, 2002 am29lv128m 17 advance information sa239 11101111 64/32 ef0000?efffff 778000?77ffff sa240 11110000 64/32 f00000?f0ffff 780000?787fff sa241 11110001 64/32 f10000?f1ffff 788000?78ffff sa242 11110010 64/32 f20000?f2ffff 790000?797fff sa243 11110011 64/32 f30000?f3ffff 798000?79ffff sa244 11110100 64/32 f40000?f4ffff 7a0000?7a7fff sa245 11110101 64/32 f50000?f5ffff 7a8000?7affff sa246 11110110 64/32 f60000?f6ffff 7b0000?7b7fff sa247 11110111 64/32 f70000?f7ffff 7b8000?7bffff sa248 11111000 64/32 f80000?f8ffff 7c0000?7c7fff sa249 11111001 64/32 f90000?f9ffff 7c8000?7cffff sa250 11111010 64/32 fa0000?faffff 7d0000?7d7fff sa251 11111011 64/32 fb0000?fbffff 7d8000?7dffff sa252 11111100 64/32 fc0000?fcffff 7e0000?7e7fff sa253 11111101 64/32 fd0000?fdffff 7e8000?7effff sa254 11111110 64/32 fe0000?feffff 7f0000?7f7fff sa255 11111111 64/32 ff0000?ffffff 7f8000?7fffff table 2. sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
18 am29lv128m december 2, 2002 advance information autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector group protection verifica- tion, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be pro- grammed with its corresponding programming algo- rithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in table 3. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2). table 3 shows the remain- ing address bits that are don?t care. when all neces- sary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in tables 10 and 11. this method does not require v id . refer to the autoselect command sequence section for more information. table 3. autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. description ce# oe# we# a22 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : amd l l h x x v id xl x l l l 00 x 01h device id cycle 1 llhxx v id xl x llh 22 x 7eh cycle 2 h h l 22 x 12h cycle 3 h h h 22 x 00h sector group protection verification llhsax v id xl x l h l x x 01h (protected), 00h (unprotected) secsi sector indicator bit (dq7), wp# protects highest address sector llhxx v id xl x l h h x x 98h (factory locked), 18h (not factory locked) secsi sector indicator bit (dq7), wp# protects lowest address sector llhxx v id xl x l h h x x 88h (factory locked), 08h (not factory locked)
december 2, 2002 am29lv128m 19 advance information sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. the hardware sector group unprotection fea- ture re-enables both program and erase operations in previously protected sector groups. sector group pro- tection/unprotection can be implemented via two methods. sector group protection/unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 25 shows the timing diagram. this method uses standard microprocessor bus cycle timing. for sector group unprotect, all unpro- tected sector group must first be protected prior to the first sector group unprotect write cycle. the device is shipped with all sector groups unpro- tected. amd offers the option of programming and protecting sector groups at its factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. table 4. sector group protection/unprotection address table sector group a22?a15 sa0 00000000 sa1 00000001 sa2 00000010 sa3 00000011 sa4?sa7 000001xx sa8?sa11 000010xx sa12?sa15 000011xx sa16?sa19 000100xx sa20?sa23 000101xx sa24?sa27 000110xx sa28?sa31 000111xx sa32?sa35 001000xx sa36?sa39 001001xx sa40?sa43 001010xx sa44?sa47 001011xx sa48?sa51 001100xx sa52?sa55 001101xx sa56?sa59 001110xx sa60?sa63 001111xx sa64?sa67 010000xx sa68?sa71 010001xx sa72?sa75 010010xx sa76?sa79 010011xx sa80?sa83 010100xx sa84?sa87 010101xx sa88?sa91 010110xx sa92?sa95 010111xx sa96?sa99 011000xx sa100?sa103 011001xx sa104?sa107 011010xx sa108?sa111 011011xx sa112?sa115 011100xx sa116?sa119 011101xx sa120?sa123 0 11110xx sa124?sa127 0 11111xx sa128?sa131 100000xx sa132?sa135 100001xx sa136?sa139 100010xx sa140?sa143 100011xx sa144?sa147 100100xx sa148?sa151 100101xx sa152?sa155 100110xx sa156?sa159 100111xx sa160?sa163 101000xx sa164?sa167 101001xx sa168?sa171 101010xx sa172?sa175 101011xx sa176?sa179 101100xx sa180?sa183 101101xx sa184?sa187 101110xx sa188?sa191 10 1111xx sa192?sa195 110000xx sa196?sa199 110001xx sa200?sa203 110010xx sa204?sa207 110011xx sa208?sa211 110100xx sa212?sa215 110101xx sa216?sa219 110110xx sa220?sa223 110111xx sa224?sa227 111000xx sa228?sa231 111001xx sa232?sa235 111010xx sa236?sa239 111011xx sa240?sa243 111100xx sa244?sa247 111101xx sa248?sa251 111110xx sa252 11111100 sa253 11111101 sa254 11111110 sa255 11111111 sector group a22?a15
20 am29lv128m december 2, 2002 advance information write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector group with- out using v id . write protect is one of two functions pro- vided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in ?sector group protection and un- protection?. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in ?dc char- acteristics?. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether the first or last sector was pre- viously set to be protected or unprotected using the method described in ?sector group protection and un- protection?. note that wp# has an internal pullup; when unconnected, wp# is at v ih . temporary sector group unprotect this feature allows temporary unprotection of previ- ously protected sector groups to change data in-sys- tem. the sector group unprotect mode is activated by setting the reset# pin to v id . during this mode, for- merly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previ- ously protected sector groups are protected again. figure 1 shows the algorithm, and figure 24 shows the timing diagrams, for this feature. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih temporary sector group unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again.
december 2, 2002 am29lv128m 21 advance information figure 2. in-system sector group protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
22 am29lv128m december 2, 2002 advance information secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 128 words/256 bytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which pre- vents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. amd offers the device with the secsi sector either factory locked or customer lockable. the fac- tory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the cus- tomer-lockable version is shipped with the secsi sec- tor unprotected, allowing customers to program the sector after receiving the device. the customer-lock- able version also has the secsi sector indicator bit permanently set to a ?0.? thus, the secsi sector indi- cator bit prevents customer-lockable devices from being used to replace devices that are factory locked. the secsi sector address space in this device is allo- cated as follows: table 5. secsi sector contents the system accesses the secsi sector through a command sequence (see ?enter secsi sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the first sector (sa0). this mode of operation continues until the system is- sues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. factory locked: secsi s ector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. a factory locked device has an 8-word/16-byte random esn at ad- dresses 000000h?000007h. customers may opt to have their code programmed by amd through the amd expressflash service. the de- vices are then shipped from amd?s factory with the secsi sector permanently locked. contact an amd representative for details on using amd?s express- flash service. customer lockable: secsi sector not programmed or protect ed at the factory as an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word/256 bytes secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. see command definitions. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2, ex- cept that reset# may be at either v ih or v id . this allows in-system protection of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 3. once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing within the remainder of the array. secsi sector address range standard factory locked expressflash factory locked customer lockable x16 x8 000000h? 000007h 000000h? 00000fh esn esn or determined by customer determined by customer 000008h? 00007fh 000010h? 0000ffh unavailable determined by customer
december 2, 2002 am29lv128m 23 advance information figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 10 and 11 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 6?9. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 6?9. the system must write the reset command to return the de- vice to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. al- ternatively, contact an amd representative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
24 am29lv128m december 2, 2002 advance information table 6. cfi query id entification string table 7. system interface string addresses (x16) data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0007h typical timeout per single byte/word write 2 n s 20h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 000ah typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0001h max. timeout for byte/word write 2 n times typical 24h 0005h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
december 2, 2002 am29lv128m 25 advance information table 8. device geometry definition addresses (x16) data description 27h 0018h device size = 2 n byte 28h 29h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 00ffh 0000h 0000h 0001h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
26 am29lv128m december 2, 2002 advance information table 9. primary vendor-specific extended query addresses (x16) data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0008h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0004h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0004h/ 0005h top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h 0001h program suspend 00h = not supported, 01h = supported
december 2, 2002 am29lv128m 27 advance information command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. tables 10 and 11 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to read- ing array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more infor- mation. see also requirements for reading array data in the device bus operations section for more information. the read-only operations table provides the read pa- rameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the de- vice entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a pr ogram or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer pro- gramming operation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. tables 10 and 11 show the address and data require- ments. this method is an alternative to that shown in table 3, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the de- vice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: a read cycle at address xx00h returns the manu- facturer code. three read cycles at addresses 01h, 0eh, and 0fh return the device code. a read cycle to an address containing a sector ad- dress (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in erase suspend).
28 am29lv128m december 2, 2002 advance information enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word/16-byte random electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system is- sues the four-cycle exit secsi sector command se- quence. the exit secsi sector command sequence returns the device to normal operation. tables 10 and 11 show the address and data requirements for both command sequences. see also ?secsi (secured sili- con) sector flash memory region? for further informa- tion. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. word/byte program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tables 10 and 11 show the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. refer to the write operation status sec- tion for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass pro- gram command, a0h; the second cycle contains the program address and data. additional data is pro- grammed in the same manner. this mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. tables 10 and 11 show the re- quirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h. the second cycle must contain the data 00h. the device then returns to the read mode. write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initi- ated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which pro- gramming will occur. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is se- lected by address bits a max ?a 4 . all subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer locations may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be per- formed across multiple write-buffer pages. this also
december 2, 2002 am29lv128m 29 advance information means that write buffer programming cannot be per- formed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter dec- rements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the pro- gram buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: load a value that is greater than the page buffer size during the number of locations to program step. write to an address in a sector different than the one specified during the write-buffer-load com- mand. write an address/data pair to a different write-buffer-page than the one selected by the starting address during the write buffer data load- ing stage of the operation. write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be written to reset the de- vice for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is re- quired when using write-buffer-programming features in unlock bypass mode. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. wp# has an internal pullup; when un- connected, wp# is at v ih . figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 18 for timing diagrams.
30 am29lv128m december 2, 2002 advance information figure 4. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq7 - dq0 at last loaded address read dq7 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see tables 10 and 11 for command sequences required for write buffer programming. (note 3) (note 1) (note 2)
december 2, 2002 am29lv128m 31 advance information figure 5. program operation program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the program sus- pend command is written during a programming pro- cess, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation has been sus- pended, the system can read array data from any non-suspended sector. the program suspend com- mand may also be issued during a programming oper- ation while an erase is suspended. in this case, data may be read from any addresses not in erase sus- pend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autose- lect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to programming. the system can deter- mine the status of the program operation using the dq7 or dq6 status bits, just as in the standard pro- gram operation. see write operation status for more information. the system must write the program resume com- mand (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ig- nored. another program suspend command can be written after the device has resume programming. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see tables 10 and 11 for program command sequence.
32 am29lv128m december 2, 2002 advance information figure 6. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during th ese operations. tables 10 and 11 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for infor- mation on these status bits. any commands written during the chip erase operation are ignored. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase op- eration is in progress. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 20 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. tables 9 & 10 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. the system must rewrite the command sequence and any additional addresses and com- mands. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
december 2, 2002 am29lv128m 33 advance information the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write opera- tion status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 20 section for timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typi- cal of 5 s (maximum of 20 s) to suspend the erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writ- ing this command. further writes of the resume com- mand are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress figure 7. erase operation notes: 1. see tables 10 and 11 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
34 am29lv128m december 2, 2002 advance information command definitions table 10. command definitions (x16 mode, byte# = v ih ) legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a22?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. bc = word count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a22?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high while the device is providing status information. 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read in three cycles. 10. if wp# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the lowest address sector, the data is 88h for factory locked and 08h for not factor locked. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 21. 12. the data is 00h for an unprotected sector and 01h for a protected sector. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. the unlock bypass command is required prior to the unlock bypass program command. 15. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume command is valid only during the erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 9) 4 555 aa 2aa 55 555 90 x01 227e x0e 2212 x0f 2200 secsi ? sector factory protect (note 10) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 12) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (note 11) 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 14) 2 xxx a0 pa pd unlock bypass reset (note 15) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 16) 1 ba b0 program/erase resume (note 17) 1 ba 30 cfi query (note 18) 1 55 98
december 2, 2002 am29lv128m 35 advance information table 11. command definitions (x8 mode, byte# = v il ) legend: x = don?t care ra = read address of the memory location to be read. rd = read data read from location ra during read operation. pa = program address. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data for location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a22?a15 uniquely select any sector. wbl = write buffer location. address must be within the same write buffer page as pa. bc = byte count. number of write buffer locations to load minus 1. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a22?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when the device is in the autoselect mode, or if dq5 goes high while the device is providing status information. 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see the autoselect command sequence section for more information. 9. the device id must be read in three cycles. 10. if wp# protects the highest address sector, the data is 98h for factory locked and 18h for not factory locked. if wp# protects the lowest address sector, the data is 88h for factory locked and 08h for not factor locked. 11. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 12. the data is 00h for an unprotected sector group and 01h for a protected sector group. 13. command sequence resets device for next command after aborted write-to-buffer operation. 14. the unlock bypass command is required prior to the unlock bypass program command. 15. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 17. the erase resume command is valid only during the erase suspend mode. 18. command is valid when device is ready to read array data or when device is in autoselect mode. command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (note 9) 4 aaa aa 555 55 aaa 90 x02 7e x1c 12 x1e 00 secsi ? sector factory protect (note 10) 4 aaa aa 555 55 aaa 90 x06 (note 10) sector group protect verify (note 12) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secsi sector region 3 aaa aa 555 55 aaa 88 exit secsi sector region 4 aaa aa 555 55 aaa 90 xxx 00 program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (note 11) 3 aaa aa 555 55 sa 25 sa bc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 13) 3 aaa aa 555 55 aaa f0 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program (note 14) 2 xxx a0 pa pd unlock bypass reset (note 15) 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend (note 16) 1 ba b0 program/erase resume (note 17) 1 ba 30 cfi query (note 18) 1 aa 98
36 am29lv128m december 2, 2002 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 12 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on suc- cessive read cycles. table 12 shows the outputs for data# polling on dq7. figure 8 shows the data# polling algorithm. figure 21 in the ac characteristics section shows the data# polling timing diagram. figure 8. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
december 2, 2002 am29lv128m 37 advance information ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 12 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approxi- mately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the de- vice enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alterna- tively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 12 shows the outputs for toggle bit i on dq6. figure 9 shows the toggle bit algorithm. figure 22 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 23 shows the differences be- tween dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii.
38 am29lv128m december 2, 2002 advance information figure 9. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce# to con- trol the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 12 to compare out- puts for dq2 and dq6. figure 9 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# sub- section. figure 22 shows t he toggle bit timing diagram. figure 23 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 9 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
december 2, 2002 am29lv128m 39 advance information other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 9). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between addi- tional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 12 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort-reset command sequence to re- turn the device to reading array data. see write buffer programming section for more details.
40 am29lv128m december 2, 2002 advance information table 12. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
december 2, 2002 am29lv128m 41 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . ?65 c to +125 c voltage with respect to ground v cc (note 1) . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9 , oe#, acc, and reset# (note 2) . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 10. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 11. 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 10. maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc (regulated voltage range) . . . . . . . . . . . . . . . . 3.0?3.6 v v cc (full voltage range) . . . . . . . . . . . . . . . . . . . . . 2.7?3.6 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65?3.6 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see ordering information section for valid v cc /v io range combinations. the i/os will not operate at 3v when v io = 1.8v 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v figure 10. maximum negative overshoot waveform 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v figure 11. maximum positive overshoot waveform
42 am29lv128m december 2, 2002 advance information dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximum input load current when wp# = v il is 5.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 6. if v io < v cc , maximum v il for ce# and dq i/os is 0.3 v io . maximum v ih for these connections is v io + 0.3 v 7. v cc voltage requirements. 8. v io voltage requirements. 9. not 100% tested. 10. includes ry/by# parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i cc1 v cc active read current (2, 3) ce# = v il, oe# = v ih 5 mhz 15 20 ma 1 mhz 15 20 i cc2 v cc initial page read current (2, 3) ce# = v il, oe# = v ih 30 50 ma i cc3 v cc intra-page read current (2, 3) ce# = v il, oe# = v ih 10 20 ma i cc4 v cc active write current (3, 4) ce# = v il, oe# = v ih 50 60 ma i cc5 v cc standby current (3) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc6 v cc reset current (3) reset# = v ss 0.3 v, wp# = v ih 15a i cc7 automatic sleep mode (3, 5) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a v il1 input low voltage 1(6, 7) ?0.5 0.8 v v ih1 input high voltage 1 (6, 7) 1.9 v cc + 0.5 v v il2 input low voltage 2 (6, 8) ?0.5 0.3 x v io v v ih2 input high voltage 2 (6, 8) 1.9 v io + 0.5 v v hh voltage for acc program acceleration v cc = 2.7?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7?3.6 v 11.5 12.5 v v ol output low voltage (10) i ol = 4.0 ma, v cc = v cc min = v io 0.15 x v io v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min = v io 0.85 v io v v oh2 i oh = ?100 a, v cc = v cc min = v io v io ?0.4 v v lko low v cc lock-out voltage (9) 2.3 2.5 v
december 2, 2002 am29lv128m 43 advance information test conditions table 13. test specifications note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels (see note) 1.5 v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 13. input waveforms and measurement levels
44 am29lv128m december 2, 2002 advance information ac characteristics read-only operations notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. 3. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . figure 14. read operation timings parameter description test setup speed options jedec std. 93r 103, 103r 113 113r 123 123r unit t avav t rc read cycle time (note 1) min 90 100 110 120 ns t av qv t acc address to output delay ce#, oe# = v il max 90 100 110 120 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 120 ns t pacc page access time max 25 30 30 40 30 40 ns t glqv t oe output enable to output delay max 25 30 30 40 30 40 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
december 2, 2002 am29lv128m 45 advance information ac characteristics * figure shows word mode. addresses are a1?a-1 for byte mode. figure 15. page read timings a22 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
46 am29lv128m december 2, 2002 advance information ac characteristics hardware reset (reset#) note: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 16. reset timings
december 2, 2002 am29lv128m 47 advance information ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation 5. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter speed options jedec std. description 93r 103, 103r 113, 113r 123, 123r unit t avav t wc write cycle time (note 1) min 90 100 110 120 ns t av wl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 100 s effective write buffer program operation (notes 2) per byte typ 2.95 s per word typ 5.9 s accelerated effective write buffer program operation (notes 2) per byte typ 2.4 s per word typ 4.7 s program operation (note 2) byte typ 50 s word typ 100 s accelerated programming operation (note 2) byte typ 40 s word typ 80 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
48 am29lv128m december 2, 2002 advance information . reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 17. reset timings
december 2, 2002 am29lv128m 49 advance information ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 18. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 19. accelerated program timing diagram
50 am29lv128m december 2, 2002 advance information ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 20. chip/sector erase operation timings
december 2, 2002 am29lv128m 51 advance information ac characteristics we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 21. data# polling timings (during embedded algorithms)
52 am29lv128m december 2, 2002 advance information ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 22. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 23. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
december 2, 2002 am29lv128m 53 advance information ac characteristics temporary sector group unprotect note: 1. not 100% tested. 2. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 24. temporary sector gr oup unprotect timing diagram
54 am29lv128m december 2, 2002 advance information ac characteristics sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih * for sector group protect, a6 = 0, a1 = 1, a0 = 0. for sector group unprotect, a6 = 1, a1 = 1, a0 = 0. figure 25. sector group protect and unprotect timing diagram
december 2, 2002 am29lv128m 55 advance information ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. ac specifications listed are tested with v io = v cc . contact amd for information on ac operation with v io v cc . parameter speed options jedec std. description 93r 103, 103r 113, 113r 123, 123r unit t avav t wc write cycle time (note 1) min 90 100 110 120 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 100 s effective write buffer program operation (notes 2, 4) per byte typ 2.95 s per word typ 5.9 s effective accelerated write buffer program operation (notes 2, 4) per byte typ 2.4 s per word typ 4.7 s program operation (note 2) byte typ 50 s word typ 100 s accelerated programming operation (note 2) byte typ 40 s word typ 80 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec
56 am29lv128m december 2, 2002 advance information ac characteristics latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 26. alternate ce# controlled write (erase/program) operation timings
december 2, 2002 am29lv128m 57 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 c, v cc = 3.0 v, 100,000 cycles. 3. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 4. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 11 for further information on command definitions. 7. the device has a minimum erase and program cycle endurance of 100,000 cycles. tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time tbd 15 sec excludes 00h programming prior to erasure (note 5) chip erase time 90 tbd sec effective write buffer program time (note 3) per byte tbd tbd s excludes system level overhead (note 6) per word tbd tbd s program time byte tbd tbd s word tbd tbd s effective accelerated program time (note 3) byte tbd tbd s word tbd tbd s accelerated program time byte tbd tbd s word tbd tbd s chip program time (note 4) tbd tbd sec parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
58 am29lv128m december 2, 2002 advance information physical dimensions ts056/tsr056?56-pin standard/reverse thin small outline package (tsop) notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 pin 1 identifier for reverse pin out (die down), ink or laser mark. 4 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 6 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 7 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8. lead coplanarity shall be within 0.10 mm as measured from the seating plane. 9 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts/tsr 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.90 14.00 14.10 13.90 0.60 0.70 0.50 3? 5? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
december 2, 2002 am29lv128m 59 advance information physical dimensions laa064?64-ball fortified ball grid array 13 x 11 mm package
60 am29lv128m december 2, 2002 advance information revision summary revision a (october 3, 2001) initial release as abbreviated advance information data sheet. revision a+1 (march 20, 2002) distinctive characteristics clarified description of enhanced versatileio control. ordering information corrected device density in device number/descrip- tion. physical dimensions added drawing that shows both ts056 and tsr056 specifications. revision b (july 1, 2002) expanded data sheet to full specification version. revision b+1 (september 16, 2002) distinctive characteristics, physical dimensions added 80-ball fine-pitch bga. product selector guide added 80-ball fine-pitch bga. added note #1. added 103, 108, 113, 118, 123, 128 regulated opns. changed all opns that end with 4 or 9 to 3 or 8. program suspend/program resume command sequence changed 1ms to 15 s maximum, with a typical of 5 s. erase suspend/erase resume commands added that the device requires a typical of 5 s. read-only operations, erase program operations, and alternate ce# controlled erase and program operations added regulated opns. changed all opns that end with 4 or 9 to 3 or 8. revision b+2 (november 11, 2002) global removed the enhanced vi/o option and changed it to vi/o only. distinctive characteristics changed the typical sector erase time to tbd. changed the typical write buffer word programming time to tbd. product selector guide removed the 98r, 108, 108r, 118, 118r, 128, and 128r speed options. replaced note #2. product selector guide a nd read only operations added a 30 ns page access time and output enable access time to the 113r and 123r speed options. ordering information modified order numbers and package markings to re- flect the removal of speed options. modified the v io ranges. added notes #1 and #2. table 4. secsi sector contents added x8 and x16 operating ranges changed the v io supply range to 1.65?3.6 v. added v io (regulated voltage range) and v io (full volt- age range). cmos compatible removed v il , v ih , v ol , and v oh from table and added v il1 , v ih1 , v il2 , v ih2 , v ol , v oh1 , and v oh2 from the cmos table in the am29lv640mh/l datasheet. erase and programming performance changed the typicals and/or maximums of chip erase time, sector erase time, effective write buffer pro- gram time, program time, and accelerated program time to tbd. customer lockable: secsi sector not programmed or protect ed at the factory. added second bullet, secsi sector-protect verify text and figure 3. secsi sector flash memory region, and enter secsi sector/exit secsi sector command sequence noted that the acc function and unlock bypass modes are not available when the secsi sector is enabled.
december 2, 2002 am29lv128m 61 advance information byte/word program command sequence, sector erase command sequence, and chip erase com- mand sequence noted that the secsi sector, autoselect, and cfi functions are unavailable when a program or erase operation is in progress. common flash memory interface (cfi) changed wording in last sentence of third paragraph from, ?...the autoselect mode.? to ?...reading array data.? changed cfi website address revision b+3 (december 2, 2002) global added sector group protection throughout datasheet and added table 4. product selector guide added v io s to table and removed note #2 ordering information corrected typos in v io ranges. removed notes #1 and 2. figure 6. program suspend/program resume change wait time to 15 s. operating ranges corrected typos in v io ranges. removed full voltage range. cmos compatible changed v ih1 and v ih2 minimum to 1.9. removed typos in notes. read-only characteristics added a 30 ns option to t pacc and t oe standard in ta- ble. added note #3. hardware reset, erase and program operations, temporary sector unprot ect, and alternate ce# controlled erase and program operations added note. trademarks copyright ? 2002 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .

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